The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a flash memory device which can improve the interfacial characteristics between a tungsten silicide layer and a polysilicon layer while reducing the resistance of the tungsten silicide layer.
Existing NOR flash memory has inherent limits to program speed. To overcome the limits, NAND flash memory devices have been proposed which can perform a data program by injecting electrons into the floating gate by Fowler-Nordheim (FN) tunneling and can provide large capacity and high integration.
A NAND flash memory device includes a plurality of cell blocks. Each cell block includes a plurality of cell strings, which contains a plurality of cells. The cells are connected in series to form a string. A drain select transistor is formed between the cell string and drain, and a source select transistor is formed between the cell string and source.
The cell of the NAND flash memory device is formed by forming an isolation structure on a given region of a semiconductor substrate, forming a gate in which a tunnel oxide film, a floating gate, a dielectric layer, and a control gate are laminated on a given region on the semiconductor substrate, and forming junction regions at both sides of the gate. The floating gate is formed using a polysilicon layer, and the control gate is formed using the polysilicon layer and the tungsten silicide layer.
As the level of integration of semiconductor devices is increased and the line width decreases, line the resistance can increase significantly. Accordingly, tungsten electrodes, which have a lower resistance than the tungsten silicide, have been developed. However, use of the tungsten electrodes presents difficulties subsequent processes. Also, tungsten tends to oxidize which results in increased resistance.
On the other hand, to reduce resistance in tungsten silicide, an additional high temperature thermal process needs to be applied after deposition. This method is also difficult to apply consistently to future devices.
In addition, if the high temperature thermal process is performed in order to reduce the resistance, the interfacial characteristics between the tungsten silicide and polysilicon (i.e., primary electrode) becomes very poor. This results from an increased grain size as the amorphous tungsten silicide is crystallized by the thermal process.
Furthermore, the tungsten silicide layer is formed in a state where the ratio of tungsten to silicon is 1:2.3 to 1:2.6. However, the ratio doubles from the thermal process and the excess silicon is moved toward the interface between polysilicon and tungsten silicide, resulting in further degradation of the interfacial characteristics. For this reason, when lines are patterned by etching the gates, failures can occur. Therefore, annealing is carried out after the gates are patterned.
However, if annealing is performed after the gates are patterned, a hard mask film is deposited on the tungsten silicide and there is a high possibility that fluorine within the tungsten silicide may diffuse into the gate dielectric layer. This causes the electrical characteristic of the gate dielectric layer to be degraded.